F1 represents the basic type, based on the Cortex-M3 core, with a main frequency of 72MHZ, and F4 represents high performance, based on the Cortex-M4 core, with a main frequency of 180M.
1. Eight working modes of GPIO
1. Pull-up input: IO port keeps high level when there is no input.
2. Pull-down input: IO port keeps low level when there is no input.
3. Floating input: In the floating input state, the level state of the IO is uncertain and completely determined by the external input. If the pin is suspended, the level of the port is uncertain.
4. Analog input: the input signal is directly connected without the Schmitt trigger, the input signal is analog instead of digital, and the other input methods input digital.
5. Push-pull output: It can output high and low levels and connect to digital devices; the push-pull structure generally means that two triodes are controlled by two complementary signals, and one triode is always turned on when the other is turned off. The high and low levels are determined by the power supply of the IC. The conduction loss is small and the efficiency is high. The output can either sink current into the load or sink current from the load. The push-pull output stage not only improves the load capacity of the circuit, but also improves the switching speed.
6. Open-drain output: the output terminal is equivalent to the collector of the triode, and a pull-up resistor is required to obtain a high level state. It is suitable for current-type driving, and its ability to absorb current is relatively strong (generally within 20mA). The open-drain circuit has the following characteristics:
(1) Use the drive capability of the external circuit to reduce the drive inside the IC. When the internal MOSFET of the IC is turned on, the drive current flows from the external VCC through the pull-up resistor, MOSFET to GND. Only a small gate drive current is required inside the IC.
(2) Generally speaking, the open drain is used to connect devices with different levels and match the level, because when the open drain pin is not connected to an external pull-up resistor, it can only output a low level. The function of outputting a high level requires a pull-up resistor. A good advantage is that the transmission level can be changed by changing the voltage of the pull-up power supply. For example, adding a pull-up resistor can provide TTL/CMOS level output, etc. (The resistance value of the pull-up resistor determines the speed of logic level conversion. The larger the resistance value, the lower the speed and the lower the power consumption, so the choice of load resistance should take into account both power consumption and speed.)
(3) The open-drain output provides a flexible output method, but it also has its weakness, which is the delay of the rising edge. Because the rising edge charges the load through an external pull-up passive resistor, so when the resistance is selected to be small, the delay will be small, but the power consumption will be large; otherwise, the delay will be large and the power consumption will be small. Therefore, if there is a requirement for delay, it is recommended to use the falling edge output.
(4) Multiple open-drain outputs can be connected to one line. Through a pull-up resistor, without adding any devices, an “AND logic” relationship is formed, that is, “wired AND”. It can be simply understood as: when all the pins are connected together, an external pull-up resistor is connected. If one pin outputs logic 0, it is equivalent to grounding, and the circuit connected in parallel with it is “equivalent to being short-circuited by a wire”. Therefore, the logic level of the external circuit is 0, and the result of AND is logic 1 only when both are high.
7. Multiplexing push-pull output: At this time, the IO is controlled by internal peripherals, such as the PWM of the timer, such as the MOSI and MISO of the SPI. For ordinary push-pull output, the IO is controlled by ODR.
8. Multiplexed open-drain output: refer to multiplexed push-pull.
2. Summarize the selection of IO mode in STM32
1. Floating input GPIO_IN_FLOATING ——floating input, which can be used for KEY identification, RX1.
2. With pull-up input GPIO_IPU——IO internal pull-up resistor input.
3. With pull-down input GPIO_IPD—— IO internal pull-down resistor input.
4. Analog input GPIO_AIN – apply ADC analog input, or save power under low power consumption.
5. Open-drain output GPIO_OUT_OD——IO output 0 is connected to GND, IO output 1 is suspended, and an external pull-up resistor is required to achieve output high level. When the output is 1, the state of the IO port is pulled high by the pull-up resistor, but because it is an open-drain output mode, the IO port can be changed to a low level or unchanged by an external circuit. It can read the IO input level change and realize the IO bidirectional function of C51.
6. Push-pull output GPIO_OUT_PP——IO output 0-connect to GND, IO output 1-connect to VCC, the read input value is unknown.
7. Push-pull output of multiplexing function GPIO_AF_PP – on-chip peripheral function (SCL, SDA of I2C).
8. Open-drain output of multiplexing function GPIO_AF_OD – on-chip peripheral function (TX1, MOSI, MISO.SCK.SS).
The main function of the RCC clock: set the system clock SYSCLK, set the AHB frequency division factor (determine how much HCLK is equal to), set the APB2 frequency division factor (determine how much PCLK2 is equal to), set the APB1 frequency division factor (determine how much PCLK1 is equal to), set each peripheral Set the frequency division factor; control the opening of the three bus clocks of AHB, APB2 and APB1, and control the opening of the clock of each peripheral. The configuration of the four clocks of SYSCLK, HCLK, PCLK2, and PCLK1 is generally: PCLK2 = HCLK = SYSCLK=PLLCLK = 72M, PCLK1=HCLK/2 = 36M. (Take stm32f103vet6 as an example)
Steps to set the system clock when using HSE
* 1. Turn on HSE and wait for HSE to stabilize
* 2. Set the prescaler factors of AHB, APB2, and APB1
* 3. Set the clock source of the PLL, and the multiplication factor of the PLL. Setting various frequencies is mainly set here
* 4. Turn on the PLL and wait for the PLL to stabilize
* 5. Switch PLLCK to system clock SYSCLK
* 6. Read the clock switching status bit to ensure that PLLCLK is selected as the system clock
[NVIC is a nested vectored interrupt controller]
1. Priority definition
There is a special register in NVIC: the interrupt priority register NVIC_IPRx, which is used to configure the priority of external interrupts. The IPR width is 8bit. In principle, the configurable priority of each external interrupt is 0~255. The smaller the value, the higher the priority. higher. However, most CM3 chips will simplify the design, so that the number of priorities actually supported is reduced. In F103, only the high 4 bits are used, and the 4 bits used to express the priority are grouped into preemptive priority and sub-priority. If there are multiple interrupts responding at the same time, the one with the higher preemption priority will preempt the one with the lower preemption priority, and if the preemption priority is the same, compare the sub-priorities. If the preemption priority and sub-priority are the same, compare their hardware interrupt numbers, the smaller the number, the higher the priority.
2. Priority grouping
The priority grouping is determined by the PRIGROUP[10:8] bits of the application interrupt and reset control register AIRCR of the core peripheral SCB. F103 is divided into 5 groups, as follows: main priority = preemptive priority.
[EXTI external interrupt/event controller]
EXTI (External interrupt/event controller)—external interrupt/event controller, which manages 20 interrupt/event lines of the controller. Each interrupt/event line corresponds to an edge detector, which can realize the detection of the rising edge and falling edge of the input signal. EXTI can realize the individual configuration of each interrupt/event line, which can be configured as interrupt or event, and the property of triggering the event.
【SysTick system timer】
SysTick—The system timer is a peripheral in the CM3 core, embedded in the NVIC. The system timer is a 24-bit downward-decreasing counter, and the time for each count of the counter is 1/SYSCLK. Generally, we set the system clock SYSCLK equal to 72M. When the value of the reload value register is decremented to 0, the system timer will generate an interrupt, and the cycle will repeat.
【Basic concept of communication】
1. Serial communication and parallel communication
According to the way of data transmission, communication can be divided into serial communication and parallel communication. Serial communication refers to a small amount of data signal wires (generally less than 8), ground wires and control signal wires between devices. A communication method that transmits data bit by bit. Parallel communication generally refers to the communication method that uses 8, 16, 32 and 64 or more data lines for transmission.
2. Full-duplex, half-duplex and simplex communication
According to the direction of data communication, communication is divided into full-duplex, half-duplex and simplex communication, which are mainly divided by the direction of the channel.
3. Synchronous communication and asynchronous communication
According to the data synchronization method of communication, it is divided into two types: synchronous and asynchronous. It can be used according to whether a clock signal is used in the communication process.
In synchronous communication, both the sending and receiving devices will use a signal line to represent the clock signal, and the two parties will coordinate and synchronize data under the drive of the clock signal, as shown in the synchronous communication in the figure. In communication, both parties usually agree to sample the data line at the rising or falling edge of the clock signal.
In asynchronous communication, clock signals are not used for data synchronization, they directly intersperse some synchronous signal bits in the data signal, or pack the main data, and transmit data in the format of data frame, as shown in the figure Some kind of asynchronous communication, some In the communication, the two parties also need to agree on the data transmission rate for better synchronization.
In synchronous communication, most of the content transmitted by the data signal is valid data, while asynchronous communication will contain various identifiers of frames, so the efficiency of synchronous communication is higher, but the allowable error of the clocks of both sides of synchronous communication is smaller , and the allowable error of the clocks of both sides of the asynchronous communication is relatively large.
4. Communication speed
A very important parameter to measure communication performance is the communication rate, which is usually expressed in bit rate (Bitrate), that is, the number of binary digits transmitted per second, and the unit is bit per second (bit/s). The concept that is easily confused with the bit rate is the “baud rate”, which indicates how many symbols are transmitted per second. In communication, symbols with the same time interval are often used to represent a binary number, and such a signal is called a symbol.
Example: In common communication transmission, 0V is used to represent the number 0, and 5V is used to represent the number 1, then one symbol can represent two states of 0 and 1, so one symbol is equal to one binary bit, and the baud rate at this time is the same as The bit rate is the same; if in communication transmission, 0V, 2V, 4V and 6V respectively represent binary numbers 00, 01, 10 and 11, then each symbol can represent four states, that is, two binary bits, so the code The number of bits is half of the number of binary bits, and the baud rate at this time is half of the bit rate. Because one symbol in many common communications represents two states, people often directly express the bit rate with the baud rate.
1. Physical layer:
There are many standards and variants for the physical layer of serial communication. We mainly explain the RS-232 standard.
According to different level standards used in communication, serial communication can be divided into TTL standard and RS-232 standard.
5V represents binary logic 1, and 0V represents logic 0; and in order to increase the long-distance transmission and anti-interference ability of serial communication, it uses -15V to represent logic 1, +15V to represent logic 0, that is, RS232.
Because the controller generally uses the TTL level standard, the MA3232 chip is often used to convert TTL and RS-232 level signals.
In the current serial communication used by other industrial controls, generally only three signal lines RXD, TXD and GND are used to directly transmit data signals, while the RTS, CTS, DSR, DTR and DCD signals are all cut off.
2. Protocol layer
The data packet of serial port communication is transmitted from the sending device to the RXD interface of the receiving device through its own TXD interface. In the protocol layer of serial port communication, the content of the data packet is specified, which is composed of start bit, main data, check bit and stop bit. The format of the data packet between the two communication parties must be consistent in order to send and receive data normally.
Baud rate: Serial port asynchronous communication, since there is no clock signal in asynchronous communication (such as the DB9 interface explained above, there is no clock signal), so the baud rate must be agreed between the two communication devices, that is, the baud rate of each symbol Length, in order to decode the signal, each grid separated by a dotted line in the basic composition of the serial port data packet in the figure represents a symbol. Common baud rates are 4800, 9600, 115200, etc.
Communication start and stop signals: A data packet of serial port communication starts from the start signal and ends with the stop signal. The start signal of a packet is represented by one data bit of logic 0, while the stop signal of a data packet can be represented by 0.5, 1, 1.5 or 2 data bits of logic 1.
Valid data: Immediately after the start bit of the data packet is the content of the main data to be transmitted, also known as valid data. The length of valid data is often agreed to be 5, 6, 7 or 8 bits long.
Data checksum: After the valid data, there is an optional data check digit. Since data communication is relatively more susceptible to external interference, resulting in deviations in transmitted data, a parity bit can be added to the transmission process to solve this problem. The parity method includes odd parity (odd), even parity (even), 0 parity (space), 1 parity (mark) and no parity (noparity).
The I2C communication protocol (Inter-Integrated Circuit) was developed by Philps. Because it has few pins, simple hardware implementation, and strong scalability, it does not require external transceivers for communication protocols such as USART and CAN.
1. Physical layer
1. Common connection methods between I2C communication devices:
Its physical layer has the following characteristics:
(1) It is a bus that supports devices. A “bus” refers to a signal line shared by multiple devices. In one I2C communication bus, multiple I2C communication devices can be connected to support multiple communication masters and multiple communication slaves.
(2) An I2C bus uses only two bus lines, a bidirectional serial data line (SDA) and a serial clock line (SCL). The data line is used to represent data, and the clock line is used to synchronize data transmission and reception.
(3) Each device connected to the bus has an independent address, and the host can use this address to access between different devices.
(4) The bus is connected to the power supply through a pull-up resistor. When the I2C device is idle, it will output a high-impedance state, and when all devices are idle, they will output a high-impedance state, and the pull-up resistor will pull the bus to a high level.
(5) When multiple hosts use the bus at the same time, in order to prevent data conflicts, arbitration will be used to determine which device occupies the bus.
(6) There are three transmission modes: the standard mode transmission rate is 100kbit/s, the fast mode is 400kbit/s, and the high-speed mode can reach 3.4Mbit/s, but most I2C devices do not support high-speed mode at present.
(7) The number of ICs connected to the same bus is limited by the maximum capacitance of the bus of 400pF.
2. Protocol layer
1. I2C basic reading and writing process
2. Communication start and stop signals
The SDA line toggles from high to low while the SCL line is high, a condition that indicates the start of communication. When SCL is high level, the SDA line switches from low level to high level, indicating the stop of communication. Start and stop signals are generally generated by the host.
2. Data validity
The SDA data line transfers one bit of data every clock cycle of SCL. During transmission, when SCL is high level, the data represented by SDA is valid, that is, when SDA is high level, it means data “1”, and when it is low level, it means data “0”. When SCL is low level, the data of SDA is invalid. Generally, at this time, SDA performs level switching to prepare for the next data representation.
Each data transfer is in bytes, and the number of bytes per transfer is unlimited.
3. Address and data direction
The I2C protocol stipulates that the device address can be 7-bit or 10-bit, and the 7-bit address is widely used in practice. One data bit following the device address is used to indicate the direction of data transfer, which is the data direction bit (R/), bit 8 or bit 11. When the data direction bit is “1”, it means that the master reads data from the slave, and when this bit is “0”, it means that the master writes data to the slave.
When reading the data direction, the host will release the control of the SDA signal line, and the slave will control the SDA signal line, and the host will receive the signal. When writing the data direction, SDA will be controlled by the host and the slave will receive the signal.
As a data receiver, when the device (regardless of master and slave) receives a byte of data or address transmitted by I2C, if you want the other party to continue sending data, you need to send an “acknowledgment (ACK)” signal to the other party, and the sender will Continue to send the next data; if the receiver wants to end the data transmission, it will send a “non-acknowledgement (NACK)” signal to the other party, and the sender will generate a stop signal after receiving the signal to end the signal transmission.
The host generates a clock during transmission. At the 9th clock, the data sending end will release the control of SDA, and the data receiving end will control SDA. If SDA is high, it means a non-acknowledgment signal (NACK), and when it is low, it means a response. signal (ACK).
The SPI protocol is a communication protocol (Serial Peripheral Interface) proposed by Motorola, namely the Serial Peripheral Interface, which is a high-speed full-duplex communication bus. It is widely used between ADC, LCD and other equipment and MCU, where a high communication rate is required.
1. SPI physical layer
Common connection methods between SPI communication devices: SPI communication uses 3 buses and chip select lines, the 3 buses are SCK, MOSI, MISO, and chip select line NSS. (SPI communication starts with the NSS line being set low, and ends with the NSS line being pulled high)
2. Protocol layer
1. Communication timing of SPI communication
2. Communication start and stop signals
The NSS signal line changes from high to low, which is the start signal of SPI communication. NSS is the exclusive signal line of each slave. When the slave detects the start signal on its own NSS line, it knows that it has been selected by the master and starts to communicate with the master. The NSS signal changes from low to high, which is the stop signal of SPI communication, indicating that the communication is over and the selected state of the slave is cancelled.
3. Data validity
The data of MOSI and MISO changes during the rising edge of SCK and is sampled during the falling edge of SCK. That is to say, at the falling edge of SCK, the data of MOSI and MISO are valid. When the level is high, it means data “1”, and when it is low level, it means data “0”. At other times, the data is invalid, and MOSI and MISO prepare for the next representation of data.
Each SPI data transfer can be in units of 8 bits or 16 bits, and the number of units per transfer is not limited.
During data transmission, MSB first or LSB first is not strictly stipulated, but to ensure that the same protocol is used between two SPI communication devices, the MSB first mode in Figure SPI communication timing is generally adopted.
4. CPOL/CPHA and communication mode
Clock polarity CPOL refers to the level signal of the SCK signal line when the SPI communication device is in an idle state (that is, the state of SCK when the NSS line is high before the SPI communication starts). When CPOL=0, SCK is low level in idle state, and when CPOL=1, it is the opposite.
The clock phase CPHA refers to the sampling moment of the data. When CPHA=0, the signal on the MOSI or MISO data line will be sampled on the “odd edge” of the SCK clock line. When CPHA=1, the data line is sampled on the “even edge” of SCK.
According to the different states of CPOL and CPHA, SPI is divided into four modes, see the four modes of SPI in the table, the master and slave need to work in the same mode to communicate normally, in practice, “mode 0” is often used with “Mode 3”
[DMA direct memory access]
DMA (Direct Memory Access)—direct memory access is a peripheral of the single-chip microcomputer. Its main function is to move data, but it does not need to occupy the CPU, that is, when transferring data, the CPU can do other things, like It is the same as multithreading. Data transfers are supported from peripherals to memory or memory to memory.
The DMA controller includes DMA1 and DMA2, of which DMA1 has 7 channels, and DMA2 has 5 channels. The channels here can be understood as a kind of pipeline for transmitting data. It should be noted that DMA2 only exists in high-capacity microcontrollers.
1. Types of storage
According to the characteristics of its storage medium, memory is mainly divided into two categories: “volatile memory” and “non-volatile memory”. Among them, “volatile/non-volatile” refers to the characteristic of whether the data content stored in the memory will be lost after the power is turned off.
2. Volatile memory – RAM memory
RAM is the abbreviation of “Random Access Memory”, which is translated as random access memory. The so-called “random access” means that when a message in the memory is read or written, the time required has nothing to do with where the information is located.
1. DRAM dynamic random access memory
The memory cell of DRAM represents data with the charge of the capacitor, with charge representing 1 and without charge representing 0. But over time, the capacitor representing 1 will discharge and the capacitor representing 0 will absorb charge, so it needs to be refreshed periodically, which is the characteristic described by the word “Dynamic”.
2. SRAM static random access memory
The storage unit of SRAM uses a latch to store data, see Figure SRAM storage unit. This kind of circuit structure can maintain the state without regular refreshing and charging (of course, if the power is cut off, the data will still be lost), so this kind of memory is called “Static (Static)” RAM.
3. Non-volatile memory
1. ROM memory: ROM is the abbreviation of “Read Only Memory”, which means a memory that can only be read. Due to the development of technology, a ROM that can easily write data was designed later, and the name “Read Only Memory” has been used.
MASK ROM: MASK (mask) ROM is the authentic “Read Only Memory”. The data stored in it is solidified by a special process at the factory and cannot be modified after production. Its main advantage is low cost in mass production .
OTPROM: OTPROM (One Time Programmable ROM) is a one-time programmable memory. This kind of memory has no data inside when it leaves the factory. Users can use a dedicated programmer to write their own data, but it can only be written once. After being written, its content cannot be modified.
EPROM: EPROM (Erasable Programmable ROM) is a rewritable memory, which solves the problem that the PROM chip can only be written once. This kind of memory uses ultraviolet rays to irradiate the chip to erase data, and erase and write must be dedicated equipment. Now this kind of memory is basically eliminated and replaced by EEPROM.
EEPROM: EEPROM (Electrically Erasable Programmable ROM) is an electrically erasable memory. EEPROM can be repeatedly erased and written. Its erasing and writing are directly controlled by the circuit, and there is no need to use external devices to erase and write. And data can be modified in units of bytes without erasing the entire chip.
2. FLASH memory
FLASH memory is also called flash memory, and it is also a rewritable memory. Some books will refer to FLASH memory as FLASH ROM, but its capacity is generally much larger than EEPROM, and when erasing, it is generally written in multiple words. Section is the unit. According to the different storage unit circuits, FLASH memory is divided into NOR FLASH and NAND FLASH.
The STM32f103 series has 3 ADCs with 12-bit resolution and each ADC has up to 16 external channels. Among them, ADC1 and ADC2 have 16 external channels, and ADC3 has different channels according to different CPU pins, and generally has 8 external channels.
STM32 has an on-chip DAC peripheral, its resolution can be configured as 8-bit or 12-bit digital input signal, with two DAC output channels, these two channels do not affect each other, each channel can use DMA function, both have Error detection capability, which can be triggered externally.
1. Classification of timers
In the STM32F1 series, in addition to interconnected products, there are 8 timers in total, which are divided into basic timers, general timers and advanced timers.
【IWDG Independent Watchdog/WWDG Window Watchdog】
1. Definition and usage scenarios of independent watchdog
Independent watchdog: It is a 12-bit down counter. When the value of the counter decreases from a certain value to 0, the system will generate a reset signal, namely IWDG_RESET. If the value of the counter is refreshed before the count is reduced to 0, then no reset signal will be generated. This action is what we often call feeding the dog.
The clock of the independent watchdog is provided by an independent RC oscillator LSI, even if the main clock fails, it is still valid and very independent. The frequency of LSI is generally between 30~60KHZ, and there will be a certain drift according to the temperature and working conditions. We generally take 40KHZ, so the timing of the independent watchdog must be very accurate, and it is only suitable for those with relatively low time accuracy requirements. occasion.
2. Definition and usage scenarios of window watchdog
Window watchdog: Like the independent watchdog, it is also a decrement counter that counts down continuously. When it is reduced to a fixed value of 0X40, if the dog is not fed, it will be reset. This value is called the lower limit of the window and is fixed. value and cannot be changed. This is similar to the independent watchdog. The difference is that the counter value of the window watchdog will be reset if it is fed to the dog before it decreases to a certain number. This value is called the upper limit of the window, and the upper limit value is determined by the user. independent settings. The value of the window watchdog counter must be between the upper window and the lower window to feed the dog.
3. Graphical watchdog
RLR is the reload register, which is used to set the counter value of the independent watchdog. TR is the counter value of the window watchdog, set independently by the user, WR is the upper window value of the window watchdog, set independently by the user.